1. Field of the Invention
This invention relates generally to the cell structure and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel and improved cell structure and improved process for fabricating a trenched semiconductor power device with reduce on-resistance.
2. Description of the Prior Art
Conventional technologies of forming a planar contact to contact both the source and body region present several technical difficulties. First, the planar source contact occupies a large space thus limiting the shrinkage of the cell dimensions. The cell density cannot be further increased due to this limitation. Furthermore, the on-resistance cannot be conveniently reduced due to the fact that for device with break-voltage higher than 30 volts, the resistance is dominated by the resistance in the drift region in the substrate below the trench. The efficiency of such semiconductor devices suffers due to the high on-resistance.
Referring to FIG. 1 for a conventional trenched MOSFET device 10 formed in a semiconductor substrate 15 with a drain region of a first conductivity type, e.g., an N+ substrate, formed at a bottom surface. The trenched MOSFET cell is formed on top of an epitaxial layer 20 of a first conductivity type, e.g., N-epi-layer that having a lower dopant concentration than the substrate. A body region 25 of a second conductivity type, e.g., a P-body region 25, is formed in the epi-layer 20 and the body region 25 encompasses a source region 30 of the first conductivity type, e.g., N+ source region 30. Each MOSFET cell further includes a N+ doped polysilicon gate 35 disposed in a trench insulated from the surrounding epi-layer 20 with a gate oxide layer 40. The MOSFET cell is insulated from the top by an NSG/BPSG layer 45 with a source contact opening to allow a source contact metal layer 50. For the purpose of reducing the ohmic resistance of the source contact 50, a P+ doped region, e.g., a Pwell region 55 is formed below the source contact formed below the source contact 55 between the source regions 30 to improve the electrical contact. The prior art MOSFET cell as shown in FIG. 1 presents at least two problems. One is the planar source-body contact 50 occupies too much space that limits further shrinkage of cell dimension for increasing the cell density. Another problem is the dominance of the resistance Rdrift in the epitaxial layer 20 below the trenched gate 30 for device with breakage voltage higher than 30 volts. The on-resistance cannot be convenient reduced due to this resistance dominance in the drift regions.
Referring to FIG. 2 for a MOSFET device disclosed by Henson in U.S. Pat. No. 6,919,599. The patented invention discloses a short-channel trenched MOS device with reduced gate charges that includes high conductivity regions formed at the bottom of its trenches and field relief regions at or below the bottom of its channel region. The structure of the MOSFET device also includes a planar contact that limits the cell density of the device due to the space occupied by the planar contact. The Rds is reduced by introducing heavier dose near trench bottom without decreasing breakdown voltage by forming additional P region underneath P-body. However, in addition to the extra space occupied by the planar contact as discussed above that limits further shrinkage of the device, such cell configurations have additional drawbacks. Specifically, the energy ion implantation in the formation process of the additional P underneath P-body through the silicon surface affects threshold voltage, and makes channel longer as result of the lateral projection in the ion implantation processes. Furthermore, the benefits of such configuration are significantly decreased when the breakdown voltage is higher than 150 volts since thickness of the epitaxial layer and the resistivity will be increased with the increase of the breakdown voltage and the Rds will be significantly increases accordingly. The heavier N doping regions formed near trench bottom and the P-body are too shallow and would not effective to significantly reduce the Rds that is mainly contributed by the increase of the resistivity caused by a thicker epitaxial layer.
Therefore, there is still a need in the art of the semiconductor device fabrication, particularly for trenched power MOSFET design and fabrication, to provide a novel transistor structure and fabrication process that would resolve these difficulties and design limitations.